The present invention relates to a semiconductor circuit with a bootstrap circuit.
Various studies on semiconductor circuits have been made recently in order to achieve higher integration density and high speed operation. Improvements in the read/write speed of a static MOS memory are particularly notable; the access time is almost comparable to that of a bipolar memory. Such improvements in the operation speed of the static MOS memory are mostly attributed to improvements in techniques of reducing the size of the MOS transistors and in circuit design of MOS transistors. For example, a semiconductor circuit which may be operated with less power consumption and at a high speed is being developed by using a bootstrap circuit, which is widely used in a dynamic semiconductor circuit, in a static semiconductor circuit.
A conventional driver circuit for driving a node having a large stray capacitance is known which uses a push-pull type inverter as shown in FIG. 1. This driver circuit has an E/D-type inverter 2 which includes a depletion-type (D-type) MOS transistor TR2 and an enhancement-type (E-type) MOS transistor TR4 and which inverts an input signal VI, and a push-pull circuit 4 which includes D-type and E-type MOS transistors TR6 and TR8 whose current paths are series-connected between power source terminals VD and VS. The input signal VI is supplied to the gate of the MOS transistors TR4 and TR6, the output signal from the inverter 2 is supplied to the gate of the E-type MOS transistor TR8, and a stray capacitor associated between the power source terminals VD and VS is charged and discharged in accordance with the output signal from the push-pull circuit 4.
The driver circuit as described above is advantageous as compared to an E/D-type inverter driver circuit in that a DC current may be made small and in that a relatively large stray capacitor can be charged with a small power consumption since a large charging current is permitted to flow only in the transient state. However, since the output stage of such a driver circuit is formed of an E/D-type push-pull circuit, a DC current will flow through this push-pull circuit.
In order to prevent the flow of such a DC current, a static bootstrap buffer circuit has been proposed which uses an E/E-type output circuit, as shown in FIG. 2, and which is capable of raising the output signal of high level to the VD level. The buffer circuit has an inverter 2 which is formed of a D-type MOS transistor TR2 and an E-type MOS transistor TR4 and which inverts the input signal VI, an output circuit 6 formed of E-type MOS transistors TR12 and TR14 whose current paths are series-connected between power source terminals VD and VS, and an E-type MOS transistor TR16 whose current path is connected between the input terminal VI and the gate of the MOS transistor TR12. The output signal from the inverter 2 is supplied to the gate of the MOS transistor TR14, and a capacitor C2 is connected between the gate of the MOS transistor TR12 and a node 8 between the MOS transistors TR12 and TR14.
When the input signal VI rises to a logic level "1" in this buffer circuit, the capacitor C2 begins to be charged. The capacitor C2 continues to be charged until the input voltage VI reaches the threshold voltage of the MOS transistor TR4 to turn on the MOS transistor TR4, and the output signal from the inverter 2 is lower than the threshold voltage of the MOS transistor TR14 to turn off the MOS transistor TR14. When the MOS transistor TR14 is turned off, the potential at the node 8 at one end of the capacitor C2 rises to a logic level "1", and the potential at the other end of the capacitor C2 rises quickly due to the bootstrap action. As a result, a voltage higher than the power source voltage VD is applied to the gate of the MOS transistor TR12 and the power source voltage VD is supplied to the node 8 through the MOS transistor TR12. Thus, the potential at the node 8 rises to the power source voltage VD. On the other hand, when the input signal VI falls to a logic level "0 ", a signal of logic level "1" is generated by the inverter 2 to turn on the MOS transistor TR14 and to discharge the capacitor C2. In this case, the MOS transistor TR12 is turned off, and no DC current flows in the output circuit 6. Accordingly, the power consumption of the buffer circuit is suppressed to the minimum.
The push-pull circuit of bootstrap-type as described above is excellent in terms of low power consumption. However, in order to operate this push-pull circuit at a high speed, the switching speed of the inverter acting as a delay circuit must be increased. When the switching speed of the inverter 2 is increased, the bootstrap action may be initiated before the capacitor C2 is sufficiently charged. If the MOS transistor TR14 is turned off in response to the output signal from the inverter 2 before the potential level of the input signal VI reaches a level of (VC - VTH) (VTH is the threshold voltage of the MOS transistor TR16), the charge on the capacitor C2 is discharged through the MOS transistor TR16 since the MOS transistor TR16 is kept on. Then, effective bootstrap action may not be obtained, and therefore, the output signal VO will rise gently. Accordingly, even if the switching speed of the inverter 2 is increased and the timing of the leading edge of an output signal VO is made earlier, the output signal VO will take a long rise time to reach a predetermined high potential level. This lowers the switching speed of the push-pull circuit.